This application claims the priority of Korean Patent Application No. 2003-73836, filed on Oct. 22, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to semiconductor integrated circuits and to a method of forming the same, and more particularly to a shallow trench isolation (STI) structure for recess channel transistors and a method of making the same.
2. Description of the Related Art
Increased packing density makes isolation techniques that electrically isolate mutually adjacent devices very important. Shallow trench isolation (STI) is a device isolation technique. In STI, a trench that defines an active region is formed in a semiconductor substrate. Then, the inside of the trench (i.e. the STI trench) is filled with an insulating material to form an isolating layer. Generally, the STI trench has a positively sloped sidewall in order to facilitate filling the trench with insulating material. Since the sidewalls of the STI trench are sloped, the width at the upper portion of the STI trench is larger than the width at a lower portion thereof. A method of forming an isolation region is disclosed in Korean Patent Laid-open No. 10-2001-0019290.
Increased packing density in semiconductor devices such as a DRAMs can result in forming a transistor with a short channel in an active region. This can result in punchthrough in a planar type transistor. Punchthrough can cause malfunctions of a highly integrated device. A recess channel transistor (RCT) can be used to achieve increased channel length. In the RCT, the channel is located along an outer periphery of a recess channel trench formed in the active region. As a result, there can be a relatively long channel.
However, if a recess channel transistor is fabricated in an active region defined by a conventional STI structure, silicon fences, (i.e., residual substrate areas) are formed on both bottom sides of the recess channel transistor. The residual substrate areas can significantly decrease the length of the channel, thereby deteriorating characteristics of the transistor. The residual substrate areas formed on both bottom sides of the recess channel transistor decrease the threshold voltage, which in turn increases leakage current.
FIG. 1a is a layout of a recess channel transistor. Referring to FIG. 1a, an active region 10 is defined by a field region 140 of the STI. A gate line pattern 20 is formed across the active region 10 and the field region 140.
FIGS. 1b, 1c and 1d are sectional views respectively taken along lines A–A′, B–B′ and C–C′ of FIG. 1a, showing a semiconductor device including a conventional STI structure and a recess channel transistor.
Referring to FIG. 1b, a recess channel trench 160 is formed within an active region defined by a STI structure 140. A recess gate 190 fills inside the recess channel trench 160, and source and drain regions 150 are formed in both sides of the recess gate 190. Thus, the recess gate 190 and the source and drain regions 150 form the recess channel transistor altogether. A channel of the recess channel transistor is formed along the outer periphery of the trench as indicated by an arrow. Accordingly, a channel length of the recess channel transistor formed in the silicon substrate 100 is longer than that of a planar-type transistor.
However, when the recess channel transistor is formed in the active region defined by the STI as shown in FIG. 1d, silicon fences, or residual substrate areas, 11 are formed on both bottom sides of the recess channel trench 160. That is, as indicated by a dot-lined circle, the silicon substrate 100 is partially left between the sidewalls of the STI structure 140 and of the recess gate 190, thereby forming the residual substrate areas 11.
If the residual substrate areas 11 are formed, channel lengths at peripheries of the active region are shortened (refer to an arrow of FIG. 1c). In other words, the channel length at the periphery of the active region (refer to FIG. 1c) becomes shorter than the channel length at the center of the active region. Since the channel length is decreased as mentioned above, a threshold voltage of the transistor is decreased, which results in increased leakage current.
FIGS. 2a and 2b are sectional views showing a method of forming a recess channel trench in an active region defined by conventional STI. FIGS. 2a and 2b are cross-sectional views, taken along line C–C′ of FIG. 1a. 
Referring to FIG. 2a, the STI structure 140 with a positively sloped sidewall is formed in a semiconductor substrate 100. The sidewall of the STI structure is positively sloped because the STI trench is formed to insure a gap fill margin. Then, a mask layer pattern that defines a recess trench is formed on the resultant structure. At this time, a mask layer is patterned such that the mask layer is linearly opened along a gate line (refer to a reference numeral 20 of FIG. 1a). Therefore, FIGS. 2a and 2b which are sectional views, taken along line C–C′, and they do not show a patterned mask layer.
As shown in FIG. 2b, anisotropic dry etching is performed to form a recess channel trench 160 using the mask layer pattern as an etch mask. Since the etch selectivity of the silicon substrate 100 relative to the STI structure 140 is large, the silicon substrate 100 in the active region is deeply etched to a depth H2 while etching the STI structure 140 by a prescribed depth H1.
The etching is carried out using the STI structure with a positive slope as a boundary. Therefore, as shown in FIG. 2b, the residual substrate areas 11 are formed on corners of a bottom surface of the recess channel trench 160. These areas greatly decreases the length of the channel at the periphery of the active region and they deteriorate characteristics of the transistor.